8051SBC V1.0

Wichit Sirichote, wichit.sirichote@gmail.com

NewMicroprocessor learning board demonstrates exemplary design of 8-bit singleboard computer.  More peripheral and easy to adapt to be a dedicatedcontroller.

I decided to rename C52EVB to be 8051SBC. Since the cpu can be any 8051 compatible chips with 40-pin DIP package. The old day chips, say 8031, 8751, 8032 or the new chips,89C51, 89C52, 89C51RD2 can be used without any problem. Some may think that your old chips were useless, now you can use it for many projects.The monitor program of new 8051SBC was placed at external 32kB EPROM. With this space, you can customize your own monitor code or even add the application program and have the DIP switch to boot it when power up. The 32kB SRAM still be mapped as external code and data memory. We can test the programin RAM, when it firmed then put it in the space in EPROM. The memory and i/o decoder is now using GAL (Generic Array Logic).

Figure1: The prototype of 8051SBC.

The hardware schematic is an exemplary design for student to learn basic design of 8-bit microprocessor board. The board is a generic tool for every microprocessor lab. I provided all materials in public domain, so you may build it for your lab. Student can learn assembly programming, HLL programming and hardware interfacing.

The new 8051SBC features;


Complete schematic for cpuand memory is shown in Figure 2. U7 is 40-pin 8051 compatible chip. Thextal is 11.0592MHz. JP1 selects internal or external code memory. Withthe external monitor mode, we make EA# to GND. The data bus D0-D7 are tiedto memory chip, U1, U2 and to the GPIO, U3, U4 directly. Both memory chipsare 32kB, so each chip needs A0-A14. A15 is used for memory decoder thatdecodes between first 32kB and second 32kB of external code memory. WhenA15 = 0, U1 the monitor rom was selected. The OE# of U1 is tied to PSEN#,so the code memory will enable only when address range 0x0000-0x7FFF ofcode memory are accessed. The upper memory space from address 0x8000-0xFFFFmakes A15 = 1. When A15 = 1, U2 or SRAM will be selected. This memory spacewas decoded to be overlapped between external data and code memory. Sowhile running under monitor mode, we can then load the hex code into theSRAM(data memory) and when JUMP from monitor program to address says 0x8000,the PSEN# that AND with RD# and ties to OE# of SRAM will enable the RAMto be code memory.

Since we have decoded thelower space, 0x0000-0x1FFF for code memory, this left a big space for externaldata memory from 0x0000-0x1FFF. The 8051SBC then borrowed this area tomake the I/O that can access as the memory space with RD# and WR# combinationwith address decoder.

We can say that this areais memory mapped I/O. U3 is an 8-bit D-FF for output port. U4 is 8-bittristate for input port. The LCD also connects cpu bus directly. To makethe I/O decoder for each chip, we use A8, A9, A10 and A15 to select eachblock. The I/O map shows the address range for each device. U6 is PLD madefrom GAL16V8. It provides the memory and I/O decoder, later you will seedetails description on how to implement the decoder.

Figure2: Complete hardware schematic, CPU, memory, PLD

Figure3: RS232, RS485, DC supply, EEPROM, ADC, RTC, keypad, debug LED.

U8 is +5V voltage regulator.D4 is protection diode. The RS232 level converter is MAX232. Notice thatwe have the RS485 transceiver as well. The TxD pin from CPU can tie toboth input, T1IN (U10) and D(U12) directly. Howvere the RxD pin is theoutput of AND logic between R1OUT(U10) and R(U12).  U11 is 32kB I2CEEPROM. It uses for program storage or the aplliaction program can useit. U9 is a popular 12-bit ADC having SPI interface. The reference voltageuses +5V. The two channels analog input has RC filter. U13 is RTC withI2C interface. It shares the I2C signal with EEPROM, U11. SW1 is 4-bitDIP swicth for system settings. User can use S3, S4, S5 and S6 for applicationprogram.


I have tested some of 40-pinDIP package 8051 compatible CPU with the 8051SBC, table 1 shows the reasonfor each chip and you may find the right for your applications.
8751old chip with ceramic packageand quartz window for UV, new generation will see how the old chip looklikes.
8031romless 8051, 128 bytesRAM
8032romless 8051, 256 bytesRAM
8052basic interpreter with EA= +VDD
AT89S8252SPI, WDT, 2kB EEPROM, 8kBFLASH, 256 bytes RAM
AT89C514kB FLASH 128 bytes RAM
AT89C528kB FLASH 256 bytes RAM
DALLAS DS500T8kB loadable RAM RTC

Table1: CPU that can be used with 8051SBC.


The reason that took me touse GAL is to reduce the number of discrete gate for memory and i/o decoder.You may noticed that, with a C52EVB, only one chip, the 74HC00 was usedfor memory and 8255 decoder. However with new 8051SBC, I need to decodethe LCD and simple port. This needs more chip, so better try with 20-pinpopular GAL from Lattice, the GAL16V8D. The GAL can emulate logic functionand can reprogram many times.

Before getting into GAL'smatter, let begin with how to replace the logic gate using logic equation.Now let see the actual decoder circuit. First take a look for memory decoder.

The EPROM will place at 0x0000to 0x7FFF. And the SRAM will place at 0x8000 to 0xFFFF. We see that wecan use A15 to be a chip select control signal for EPROM directly. Whereasfor the SRAM it needs to invert A15 in order to select SRAM when A15 becomes'1' for address 0x8000-0xFFFF.

Note * is active low signal.

To read or fetch the contentof EPROM, the place we store monitor program, we must provide *PSEN signaltied to output enable pin.

However for SRAM, we willuse it for user program running as well as the place where we can editthe machine code, so we must make it to be code and data memory space.This can be made easily with *RD and *PSEN logical AND together. The circuitwould be,

A bit complicate for i/o decoder,as shown below we see the popular decoder chip, the 74LS138, 3-to-8 linedecoder and some gates were used to provide control signal for the i/odevices. The i/o space uses the external data memory with address 0x0000to 0x7FFF. A15 must be low to enable the output of 74LS138. A8-A10 selectsthe active low output for each i/o.

Let look at the first device,the LCD. Y0 will active low when all inputs are low, or A8-A10 and A15= '0'. The datasheet of LCD says, the signal E of LCD will active for bothread or write cycle, so we AND them together with U5B. U6B provides thepositive pulse when Y0 and pin 6 of U5B low. This signal, LCD_E can thendirectly tie to signal E of the LCD.

Similarly for GPIO1 or 74HC573,latch signal. Now GPIO1 uses Y1, that means A8 must be '1', A9,A10 andA15 must be '0'. The WR signal is logical OR with Y1. The NOR gate U7Bprovides the positive pulse similar to the LCD_E signal. This signal willcontrol the D FF latch. Dada is loaded into FF and the is latched at highto low transition.

For the input port made bytri-state buffer, 74LS244, the enable signal was made by Y2 and RD signal.However now A9 must be '1' and A8, A10 and A15 must be '0'.

With above decoder, we thenneed more chips to make it. Now let see how the GAL chip looks like.


 The GAL chip was Lattice GAL16V8D. The GAL is a programmable logic device(PLD). We can write the logic equation, convert it to JED file and programthe GAL with JED file. Then we can replace above circuit with single GALchip. The GAL16V8 has 10 inputs and 8 outputs. The chip can reprogram manytimes. In this design I used only one chip to replace such memory and i/odecoder circuit.

UsingPLD Assembler

To implement the logic withGAL, we must first edit the logic equation and have the PLD assembler totranslate the equation file to JEDEC file. I found OPALjr2.0 from google search. It's very easy to use. Now let see theequation of above decoder.
; 8051SBC PLD Equation
; Memory and I/O decoderfor 8051 Single Board Computer
; Wichit Sirichote, kswichit@kmitl.ac.th
; May 1, 2003
; PLD: Lattice GAL16V8D


 a15=1 rd=2 wr=3 a8=4a9=5 a10=6 rs232=7 rs485=8 psen=9 rom_ce=12
 ram_ce=13 ram_oe=14rom_oe=15 lcd_e=16 gpio1=17 gpio2=18 rxd=19


ram_oe = rd * psen

rxd = rs232 * rs485

rom_ce = a15

ram_ce = /a15

rom_oe = psen

/lcd_e = rd * wr + a8 + a9+ a10 + a15

/gpio1 = /a8 + a9 + a10 +a15 + wr

gpio2 = a8 + /a9 + a10 +a15 + rd 

Note. * is logical AND, +is logical OR and / is logical NOT.

There is some i/o pin availableon GAL, I also used them for sharing between rs232 and rs485. The outputis tie to RxD pin of the cpu. See schematic for detail.

When finish editing the equationfile, click MODULE -> EQU2JED, it will convert the equation file to JEDECfile. Let look at the output JEDEC file.
EQN2JED - Boolean Equations to JEDEC file assembler (Version V101)
Copyright (c) National Semiconductor Corporation 1990-1993
Assembled from "D:\C52EVBV3\O\8051SBC.EQN". Date: 5-1-103
NOTE PINS a15:1 rd:2 wr:3 a8:4 a9:5 a10:6 rs232:7 rs485:8 psen:9*
NOTE PINS rom_ce:12 ram_ce:13 ram_oe:14 rom_oe:15 lcd_e:16 gpio1:17*
NOTE PINS gpio2:18 rxd:19*

The JEDEC file is standardfile for any GAL programmer. I used GALBLASTtoprogram it.

Before you can use GAL orany PLD efficiently, you must have knowledge on the fundamental of digitallogic. The PLD is just to help hardware design more easy.

12-bitADC converter

I found Microchip 12-bitADC converter, MCP3202 that can replace Linear Technology LTC1298 directly.Below is pin diagram of 8-pin DIP package. MCP3202 is cheaper than LTC1298.Both chips are pins compatible. The 8051SBC can use either one withoutany problem.


With the external 32kB EPROM,the 27C256, we then need the EPROM programmer. I used willemEPROM programmer. Also here in Thailand http://se-ed.net/mpu51/Youmay build it easily. Later I'll add the EPROM programmer attach to the8051SBC.

The main monitor code spaceis approx. 8kB. This fits exactly in 89C52 chip. So you can add many thingsinto 32kB EPROM. During firmware developing, I used parallel eeprom, 28C256from ATMEL. I made the adapter from two sockets. The socket swaps pin 1and pin 14. If you have the 28C256, you can use my idea.

Some may got many ceramicEPROM, 27C256. To erase it, you need Ultraviolet light. When your codefirms, you can write the program into a cheap 27C256 OTP (One Time Program).

The monitor program composesof three files.

2. myextra1.ASM
3. new.c

The 8051SBC.ASM and myextra1.asmare modified version of PAULMON2 free monitor program written by Paul Stoffregen.Both files fit in 8kB space. The new commands is now under developing withMicro-C compiler. The available for download was tested on RAM and thenrecompile with MEDIUM memory model. In addition to such monitor code, Ialso experimented with Camel FORTH. EEPROM booting still working with thisversion excepts the boot switch is now move to DIP switch bit 0. To startCemel FORTH, when set DIP switch bit 1 to '0' after power up, it will enterCamel FORTH.

The Intel hex file for themonitor program including new commands and Camel FORTH is here, 8051SBC.HEX.

Below is the sample of newcommands.
8051SBC Microprocessor LearningBoard

ADDR:8000> Help

Standard Commands
  ?- This help list
  M- List programs
  R- Run program
  L- Download
  U- Upload
  N- New location
  J- Jump to memorylocation
  H- Hex dump externalmemory
  I- Hex dump internalmemory
  E- Editing externalram
  C- Clear memory
User Installed Commands
  D- Disassemble
  S- Single-Step
  Q- Quick home


Notice that letter D is nowchanged to Disassemble, and L changed Load Intel hex file. Command Q willget back to address 0x8000. Z command still exists. Now let see new commandwith letter W.

8051SBC new commands (press? for help or q to quit)


Help Menu
D Dec2Hex
R Read GPIO2
Q Quit
I i/o address
B Binary image
? help

>>Decimal to Hex converter

Enter decimal number = -32768
Dec -> Hex -> Bin
-32768 -> 8000 -> 1000000000000000

>>Read GPIO2 (8-bit inputport)

FD 11111101

>>i/o address decoded byPLD

LCD   command write    0x0000
LCD   data write       0x0001
LCD   commandread      0x0002
LCD   data read        0x0003
GPIO1 8-bit output port0x0100
GPIO2 8-bit input port 0x0200
expansion i/o space    0x0300-0x07FF


Now let make DIP switch bit1 to '0' and then power up the board.
8051 CamelForth v1.6 27Mar 2000
2a emit *ok
: star 2a emit ; ok
star *ok

The sample above is a common first word for FORTH beginner. We define word 'star' with 2a put to data stack and emit it to screen. I used to try FORTH with my design 80C88, since I was a student in 1984. However the Harvard architecture of 8051 may not suitable to make use of FORTH more efficient. The reason why I added FORTH to the 8051 board is just to experiment the startup booting.


I found some board has a problem on serial port. When power up the board, the prompt was printed on screen repeatedly. I fixed it by adding a 4.7k pull-up resistor at pin 1 of 75176 RS485 driver. See the picture below.

Monitorprogram 8051SBC.asm
IntelHex files mypaulm2.hex
IntelHex file (three files) 8051SBC.hex
8051SBC Reference Manual8051SBCreference.pdf
PCB gerber files8051gerber.zip
OrCAD 9.1 MAX file8051sbc.max
OrCAD 9.1 Schematic andNetlist filesorcad8051sbc.zip
8051SBC BOMbom8051sbc.txt
Equation and JEDEC filefor GAL16V8D8051sbc.eqn

Contribution to 8051SBC

If you like my new design of 8051 kit with hex keypad, please have a look, 8051 Microcontroller Kit

30 Nov 2003

Recovered 16 December, 2015