68k Single Board Computer

Wichit Sirichote, wichit.sirichote@gmail.com

Build a 32-bit power single board computer. The board fetures 68HC000 @ 8MHz, 256kB FLASH, 256kB SRAM. Available now schematic of DTACK and decoder for CPLD.
Finally I got the problem with the limited resource of 8-bit microprocessor. One of my experiment needs the computing power between 8-bit and 32-bit cpu.For 8-bit applications I use MCS51 and AVR. Whereas the 32-bit applications,I used embbeded PC running linux. So I chose the cheap 32-bit cpu from Motorola, the 68HC000. The chip is quite old but there are many chip makers still produce it. I like the addressing modes of 68000 cpu. So I spent my hobby time, design the hardware and develop a simple monitor program.

Figure1: Prototype of the 68k Single Board Computer (click image for larger photo).

The 68000 Single Board Computer features:

Hardware descriptions

Figure 1 shows the complete hardware schematic of the 68k SBC. U1 is 68-pin PLCC 68HC000 CMOS cpu.Y1 is 8MHz oscillator module. The reset signal is generated by power onreset chip, MCP120. The 16-bit data bus, D0-D15 are tied to memory chips directly. D0-D7 are tied to odd byte and D8-D15 to even byte. As can be seen in the schematic, I used 512kB FLASH, 29C040. It needs A1-A19 address lines. But the prototype used only 128kB FLASH, 29C010. It needs only A1-A17.Since the 29C0101 does not use pin 30 and 1, so we can put it to the board without the need of modification.

Figure2: Complete schematic of the 68k Single Board Computer.

Similarly for SRAM interface, but if the 128kB SRAM was used instead of 512KB, the layout needs to modify at pin 30. For 128kB SRAM this pin must tie to +5V. For odd and even bytes,the signal wiring of data bus is the same as FLASH. U9 CPLD Xilinx 9572 provides the memory decoder and DTACK genration signals. It can replace a number of glue logic. The schematic files for U9 is test1.sch and the Xilinx foundation software will produce the JEDEC file from the schematic.You may learn from test1.sch for the details of how DTACK and some of the glue logic work.

U11 is for simple memory mapped I/O decoder signals. The schematic file is 68kio.sch. U13 and U14are 8-bit input/output ports. The serial port is 6850 UART. It provides terminal interface with 9600 8n1 format. The clock for TxD and RxD is 153600Hz.Since the 6850 needs 16x frequency to give 9600 BAUD. The divider implemented by U9 is (8MHz/13)/4 or 153846Hz. This frequency gives BAUD = 153846/16=9615, which is correct for 9600 BAUD.

XilinxXC9572 CPLD

I used Xilinx foundation software F2.1i, Build 3.1.162 for CPLD programming. The software include IDE for schematic editor, simulator, compiler and JTAG programmer. As seen in the schematic JP1 and JP2 are 8-pin JTAG headers.

Monitor Program: Commands

The monitor program was developed using C32. The 68k SBC connects the host PC via 9600 serial interface. The terminal software is TeraTerm VT100 emulator. Figure 3 shows the help menu when power up the board.

Figure3: Startup menu of zBug V1.0.

You may load the Motorola s-record and jump from monitor to application program in RAM.

zBug V1.0 for 68000-Based SingleBoard Computer (press ? for help)

100000>load Motorola s-record (accepts2 and s8) quit: ESC

                           SEnding file D:LED.HEX

188 bytes loaded, 0 records checksumerror

100000>jump to user program 100400>110000

Figure4: Load s-record and jump to application program.

The command 's' displays user STACK content with 16-word depth.

100000>stack (user)'s content, shows16-WORD deep

      1370D4 [D05C]
      1370D6 [21B0]
      1370D8 [2805]
      1370DA [E100]
      1370DC [16A8]
      1370DE [BA20]
      1370E0 [20AA]
      1370E2 [60E1]
      1370E4 [A01E]
      1370E6 [A429]
      1370E8 [C2E1]
      1370EA [C531]
      1370EC [2760]
      1370EE [6A11]
      1370F0 [0011]
      1370F2 [0020]
TOS--->1370F4 [1C73]


Figure5: User STACK display with command 's'.

The command 'd' will disassemble the machine code into nmemonics.

110000>disassemble machine codeto mnemonic

110000    41F900700001        LEA.L   $00700001,A0
110006    207C00700001        MOVE.L  #7340033,A0
11000C    615A                    BSR.S   $110068
11000E    103C0001              MOVE.B  #1,D0
110012    343C0003              MOVE.W  #3,D2
110016    4600                     NOT.B   D0
110018    1080                     MOVE.B  D0,(A0)
11001A    4600                     NOT.B   D0
11001C    61000040              BSR.L   $11005E
110020    E318                     ROL.B   #1,D0
110022    0839000000600001  BTST    #0,$00600001
11002A    6626                     BNE.S   $110052
11002C    51CAFFE8              DBF.L   D2,$110016
110030    343C0003              MOVE.W  #3,D2
110034    4600                     NOT.B   D0
110036    1080                     MOVE.B  D0,(A0)
110038    4600                     NOT.B   D0
11003A    61000022               BSR.L   $11005E
11003E    E218                     ROR.B   #1,D0
110040    0839000000600001  BTST    #0,$00600001


Figure 6: Disassemble machine code (based on tutorX68) into mnemonics with command'd'.

MonitorProgram: source code

The monitor source code isT68K.ASM. While I was developing the software, I found the tool to helpsplit the binary image into two files, i.e. odd and even bytes files. So when assemble the source code, I must let the assembler produced BIN image file. With C32 Cross Assembler V3.0, we can use directive HOF as follows;

CPU    "68000.TBL"      ; CPU TABLE
HOF    "BIN16"          ; HEX OUTPUTFORMAT

To assemble the T68k.asm, we type command line as follows;

d:\c32\c32T68k.asm -h T68k.bin -l T68k.lst

The output file is T68k.bin will be binary image! Now we can use SPLIT2.exe to split it into ODD and EVN files.


Inputsource file name: t68k.bin
Outputeven file name[t68k.EVN]:
Outputodd file name[t68k.ODD]:

File will be splitted to t68k.EVN,t68k.ODD
2 ways splitting now...


Those files, ODD and EVN files can then be programmed to the FLASH memory using a given EPROM programmer easily. I used Willem's EPROMER to program the FLASH chip AT29C010.

Now What isthe RAM file, U68K.ASM for monitor porgram?

It is the same monitor program but it was relocated from ROM address to RAM space, so developer can write new command and test the code before switch it to ROM space.

Now we can produce Motorola s-record, no need to split it. Since it can download to RAM and test run under the main monitor program. We use HOF "MOT16" instead.

  CPU     "68000.TBL"      ;CPU TABLE
 ; HOF     "BIN16"         ; HEX OUTPUT FORMAT

You may study the vector address of reset and interrupts to see the offset setting between ROM and RAM version. After download the u68k.hex into RAM,you can reboot in RAM mode monitor by command 'b'.
100000>load Motorola s-record (accepts2 and s8) quit: ESC

                           SEnding file D:U68K.HEX

11205 bytes loaded, 0 records checksumerror


zBug(RAM) V1.0 for 68000-Based SingleBoard Computer (press ? for help)


Figure 7: Boot in RAM mode for monitor code developing.

You may noticed now, the title message shows zBug(RAM) instead of zBug V1.0.

To exit the RAM mode, just press reset key.

When the test is OK, you may change the location of start program from ORG RAM+0 to ORG 0.


  ORG RAM+$24

  ORG RAM+$80
---------------------------------------------------------------------------------------U68k.asm ----------------------------------------------
  ORG 0

  ORG $24

  ORG $80

Note:Remember the split2 needs binary image, not hex file, so you must produce the BIN file from T68k.asm using,

d:\c32\c32T68k.asm -h T68k.bin -l T68k.lst

Then program the bin file for odd and even FLASH. Put the odd into D0-D7and even to D8-D15 sockets!


I got many requests on VHDL or schematic designed for XC9572 CPLD. I have captured the schematic and provided the schematic in GIF files. You may learn how do I design DTACK generation, decoder, UART clock. Click at the picture below for GIF zip file.

Figure 8: Schematic design of DTACK, decoder, clock for UART and VME.

Schematic 68ksbc.pdf
Test program LED.ASMLED.HEX
zBug V1.0 Monitor program (ROM file) T68K.ASM
zBug V1.0 Monitor program (RAM file)
start address is $100400
Disassembler code and IMAGE file (in zip file) DIS.ASM
BIN file of zBug V1.0 T68K.BIN
Program that splits BIN file into ODD and EVEN files SLIT2.EXE
monitor BIN file for ODD and EVEN bytes, (in zip files) T68K.ODD
OrCAD 9.1 Schematic, BOM orcad68k.zip
OrCAD 9.1 MAX and gerber files 68kgerber.zip
Schematic and JEDEC files for CPLD with Xilinx foundation F2.1i, Build 3.1.162
test1.sch for U9 and 68kio.sch for U11
schematic of DTACK and decoder for XC9572 CPLD (GIF files) CPLD_schem.zip
Hi resolution image of the prototype board 68khires.jpg

Download hex files in zip format, 68khex.zip

Note: The author suggests those who interested in building the 68k board should study "Programming and Designing with the 68000 Family" written by Tibet Mimar beforehand.


Last updated 24 February 2020

Recovered, 16 December 2015

2 April 2004